Chip bonding: the "art of soldering" in the microscopic world?

CMOS chip wire bonding failure analysis and process improvement technical report

In the development of microelectronic packaging technology, wire bonding technology has always played an indispensable role. As a key process connecting the chip's internal circuit with the outer packaging substrate, its quality directly determines the electrical performance and long-term reliability of the integrated circuit. According to industry research data, the global annual chip scrap loss due to bonding failure exceeds 1.2 billion US dollars, of which CMOS chips have a 30%-40% higher incidence of bonding failure than other types of chips due to the particularity of multi-layer wiring structure.

At present, the research on wire bonding technology in academia and industry focuses on the development of new bonding materials and the optimization of process parameters, while the systematic research on the damage mechanism of pads during the bonding process is relatively weak. In actual production, the rework rate caused by the peeling and "crater" phenomenon of CMOS chip bonding pads is generally maintained at 15%-20%, and the production data of a large domestic chip foundry shows that such failures will reduce the average daily production capacity of each production line by 300-500 pieces, and the direct economic loss will reach 23,000 yuan per day.

Based on the statistical analysis of more than 3000 groups of failure cases, combined with high-resolution microscopic characterization and finite element simulation technology, this study constructs a full-chain research system of "fault phenomena-influencing factors-mechanism-optimization scheme". Through the in-depth analysis of the two typical failure modes of bonding pad spalling and "crater", a targeted process improvement scheme is proposed, and through strict reliability verification, it provides systematic technical support and reliability guarantee for CMOS chip wire bonding technology.

1. Microscopic characterization of typical failure modes of bonding pads

The mechanical damage during the wire bonding process of CMOS chips presents two completely different failure forms, and their microscopic characteristics and evolution laws can be clearly revealed through multi-dimensional microscopic analysis:

1.1 Grading characteristics of bonding pad peeling

The spalling of the bonding pad is the interface separation between the aluminum metal layer and the underlying insulation material, which can be divided into three levels according to the degree of damage:

Mild peeling (Grade I): Macroscopic features: 0.5-1μm uplift at the edge of the bond point visible under light microscopy (50x), like a slight curl at the edge of the paper; Microscopic manifestations: Scanning electron microscopy (SEM) observation showed that gaps began to appear between the aluminum layer and the BPSG layer, but did not form a continuous peeling band; Impact assessment: The bond strength decreases by about 5%-10% at this time, but the electrical properties have not been significantly affected. Moderate exfoliation (grade II.): macroscopic features: peeling area extends radially, forming a 10-50μm tear band, showing obvious "crescent-shaped" defects under light microscopy; Microscopic performance: SEM images show significant plastic deformation traces at the edge of the aluminum layer, with an elongation of 15%-20%. Impact assessment: Bond strength decreases by 30%-40%, contact resistance begins to fluctuate (rate of change > 10%). Severe peeling (Grade III): Macroscopic characteristics: The metal layer and the lead bonding point are separated from the pad, exposing the off-white BPSG insulation layer below, and the peeling surface is typical step-shaped. Microscopic performance: Energy dispersive X-ray spectroscopy (EDS) analysis showed that the oxygen content at the peeled interface reached 35%-40%, which was in line with the compositional characteristics of BPSG material. Impact assessment: Bond strength decreased by more than 70%, and some samples experienced intermittent open circuits. Statistics from a chip foundry show that the incidence of level III peeling in CMOS chips with 7-8 layers of wiring is 120ppm, which is significantly higher than the 45ppm of 3-4 layer wiring chips, indicating that the multi-layer wiring structure is an important factor leading to insufficient pad adhesion.

1.2 Morphological analysis of the "crater" phenomenon

"craters" belong to the deeper level of material damage, and their formation process has typical brittle fracture characteristics, which can be divided into two categories according to the depth of the pit: superficial "craters" (< 2μm deep): Morphological characteristics: irregular funnel-shaped under light microscope, usually 5-10μm in diameter, with fine cracks (length < 3μm); Microscopic manifestations: SEM observation showed that the bottom of the pit was relatively flat, and there were a small number of silicon particles attached (particle size 0.5-1μm). Formation mechanism: It is mainly caused by plastic deformation caused by local stress exceeding the yield strength of silicon. Deep "craters" (2-5μm depth): Morphological characteristics: up to 10-20μm in diameter, edge crack length >5μm, some cracks can extend inside the chip; Microscopic manifestations: high-power SEM showed obvious cleavage surfaces at the bottom of the pit, and electron backscatter diffraction (EBSD) analysis confirmed fractures along the <111> crystal plane. Formation mechanism: Brittle fracture caused by stress concentration caused by silic node tumors, often accompanied by dissociation of silicon crystals. Comparative experiments show that the incidence of "craters" on chips with silic nodes is 8-10 times higher than that of normal chips, and when the bonding pressure is > 30g, the proportion of deep "craters" increases from 20% to 60%, indicating that silic nodes and excessive bonding force are the key factors leading to severe "craters". Correlation analysis of the two failure modes showed that 35% of the samples in the same batch of failed chips had both spalling and "crater" characteristics, indicating that the influencing factors of these two types of failure had a significant intersection, often the result of a combination of factors.

2. Multi-factor coupling mechanism of bond failure

CMOS chip bond failure is the result of the coupling of multiple factors such as chip structure, material properties, and process parameters, and the contribution of each factor can be quantified by designing orthogonal experiments and failure tree analysis (FTA):

2.1 Mechanical influence of chip structural defects

The multi-layer wiring structure of CMOS chips makes their bonding pads a typical "weak link", with key risk points including:

Stress concentration effect of silic nodes: Formation mechanism: During chip fabrication, silicon substrates may produce micron-scale silicon crystalline particles (1-5μm in diameter) during high-temperature diffusion (>1000°C), which are deposited under the aluminum pad in subsequent processes;

Finite element simulation: When bonding pressure is applied, silacts as a "miniature indenter", generating local stresses of up to 800-1000MPa at the contact point, far exceeding the breaking strength of silicon (about 700MPa). Failure threshold: Experiments have shown that when the silica node is > 3 μm in diameter and < 2 μm from the pad surface, the incidence of "craters" surges to 2.3%, which is 15 times more than normal. Material differences in pad bonding force: Structural comparison: The bonding area between the 100μm ×100μm pad and the BPSG layer of CMOS chips accounts for more than 90%, while the bonding area of the same size pad and metal vias of GaAs chips accounts for >85%.

Nanoindentation test: The bond strength of the aluminum-BPSG interface is only 20-30MPa, while the bond strength of the aluminum-metal interface can reach 100-150MPa, which is only 1/5-1/3 of the latter; Failure probability: This structural difference results in CMOS chips having a 4-6 times higher chance of pad peeling than GaAs chips under the same bonding force. Buffering effect of metallized layer thickness: Quantitative relationship: Experimental data show that when the thickness of the aluminum layer increases from 0.8μm to 2.0μm, the incidence of "crater" decreases from 1.2% to 0.3%, showing a significant negative correlation (correlation coefficient R=-0.92). Mechanism of action: The thicker metal layer can absorb 30%-40% of the ultrasonic energy through plastic deformation, reducing the stress transferred to the underlying silicon; Process Limitations: Due to the limitations of lithography accuracy, the aluminum layer thickness of CMOS chips at the sub-7nm node is typically ≤ 1.2μm, which makes the risk of bond failure higher for advanced process chips.

2.2 Matching analysis of bonding material properties

The material properties of the bonding tool and lead directly affect the energy transfer efficiency, and mismatched material combinations can significantly increase the risk of damage:

Optimization interval of splitting knife structure parameters: rod length effect: Vibration theory analysis shows that for every 1mm increase in the length of the splitting rod, the tip amplitude increases by about 5%-8%. When the rod length is increased from 10mm to 14mm, the pad damage rate increases from 0.5% to 2.1%; Face angle: The splitting knife at 8°FA (face angle) has a more uniform stress distribution than 15°FA, and the experiment shows that the incidence of spalling is reduced by 60%; Material selection: The elastic modulus (600-650GPa) of tungsten carbide (WC) splitting knives is 2 times that of ceramic splitting tools (300-350GPa), which is more suitable for rigid wire bonding but is more sensitive to process parameters. Quantitative relationship between lead hardness and energy demand: Empirical formula: According to E=K (HT)^(3/2) (K is constant, H is Vickers hardness, T is metal thickness), aluminum wire (H=50-100HV) requires 2-3 times more ultrasonic energy than gold wire (H=20-30HV); Practical impact: When using 50HV aluminum wire, the ultrasonic power needs to be increased from 60mW to 150mW of the gold wire to achieve the same bond strength, resulting in a 3-fold increase in the damage rate of the pads. Compromise: 25μm gold wire (hardness 220N/mm²) While maintaining strength, the energy requirements are only 40%-50% of the same specification aluminum wire, making it ideal for balancing performance and reliability.

2.3 Synergy of process parameters

There is a complex interaction between the energy input parameters in the bonding process, and the optimal parameter window can be determined by the response surface analysis method: Double threshold characteristics of bonding force: too low risk: when the bonding force is < 15g, the contact between the splitting knife and the pad is insufficient, forming a "point contact", and the local stress concentration leads to an increase in the "crater" rate. Excessive risk: At > 30g, the interlayer shear stress exceeds the bonding strength, and the peeling rate increases exponentially. Optimal interval: 20-25g was determined to be the safe range, and the total incidence of both failures was < 0.3%. The transmission law of ultrasonic energy: Power impact: 60mW is the critical value, after exceeding this value, the risk of failure increases by 40% for every 10mW increase;

Time effect: Within 30ms, the bonding strength increases with time. After more than 30ms, the strength stabilizes but the risk of damage increases; Frequency matching: The 20kHz ultrasound frequency is close to the natural frequency of the CMOS chip (about 18-22kHz), which is prone to resonance amplification effect, leading to aggravated damage. Indirect effects of temperature: softening: the yield strength of aluminum drops to 60% of room temperature at 150°C, which can reduce the energy required for bonding; Interfacial Diffusion: High temperature promotes the diffusion of gold-aluminum atoms, forming a continuous IMC layer (thickness 50-100nm) at 200°C in 30ms; Limitations: Exceeding 250°C will cause the BPSG layer to soften and flow, so the thermal ultrasonic bonding temperature should be controlled at 150-200°C.

2.4 The impact of uncertainty in the operation process

The proportion of failures caused by human factors is about 10%-15%, mainly including: Positioning deviation: When the center of the bonding point and the center of the pad are offset by more than 10μm, the edge stress increases by 2-3 times; Impact speed: A tool drop speed of > 5mm/s produces an instantaneous impact force, which has been experimentally shown to increase the "crater" rate from 0.4% to 1.8%; Inadequate maintenance: Splitting knife wear (tip radius > 5μm) leads to uneven energy distribution, increasing the risk of failure by 50%.

3. Systematic optimization scheme of the bonding process

Based on the failure mechanism analysis, the solution is constructed from three dimensions: material selection, parameter optimization, and equipment modification:

3.1 Matching design of bonding material and tool: Comparison of scientific selection performance of lead materials: 25μm gold wire (purity 99.99%) has the best comprehensive performance, and its breaking strength (140MPa) and elongation (30%) are better than that of aluminum wire of the same specification (100MPa, 15%).

Cost balance: Although the price of gold wire is 8 times that of aluminum wire, it can increase the qualification rate by 15% and reduce the overall cost by 7%-10%;

Reliability advantages: High-temperature storage tests show that the rate of change of contact resistance of gold wire bonding (<5%) is much lower than that of aluminum wire (>15%).

Customized parameters of the splitting knife: Structural parameters: determine the combination scheme of 12mm rod length, 8°FA, and 25.4mm OR (outer radius), which reduces the energy transfer loss by 35% compared with the standard splitting knife; Surface treatment: Diamond-like coating (DLC) is used to reduce the coefficient of friction from 0.6 to 0.2 and reduce lateral shear force; Life management: Set 500,000 bonds as a replacement threshold, at which time the wear of the splitting knife is < 2μm, which can ensure energy transfer stability.

3.2 Experimental design and verification of parameter optimization

The optimal process parameters were determined by using a three-stage optimization strategy: single-factor screening stage: variable range: ultrasonic power 40-80mW, time 10-50ms, bonding force 15-35g; Evaluation indicators: bonding strength (target ≥ 15g), ball shear force (target ≥30g), failure rate (target < 0.5%); Preliminary results: 60-70mW, 25-35ms, and 20-25g were identified as candidate intervals.

Orthogonal test optimization stage: experimental design: L9 (3³) orthogonal table, 3 factors and 3 levels; Statistical analysis: Analysis of variance showed that ultrasonic power had the most significant effect on failure (contribution rate 45%), followed by bonding force (30%). Optimal combination: 60mW power, 30ms time, 25g force, at this time the bond strength is 18.5g, the shear force is 35.2g, and there is no failure. Robustness verification stage: parameter fluctuation: adjust within the range of ±10% of the optimal value, verify the process window; Chip differences: 3 batches of different batches of chips are selected for testing to ensure the universality of the scheme. The results confirmed that the average failure rate was 0.08% for 500 pieces of continuous production, which was 94% lower than before optimization.

3.3 Adaptability selection of bonding methods

Technical advantages of automatic gold ball thermosonic bonding: Flexibility: The first bonding point can be adjusted by 360° rotation to adapt to different pad layouts;

Reliability: The contact area of ball bonding is 2-3 times that of wedge bonding, and the stress distribution is more uniform; Increased efficiency: The bonding speed of the automatic system is 2-3 threads per second, which is 5 times faster than manual operation.

4. Reliability verification of optimized processes

Evaluate the long-term reliability of the optimization scheme through accelerated environmental testing:

4.1 Test conditions and monitoring indicators

Environmental test combination scheme: high temperature storage: 125°C/168h, simulating the thermal aging effect of long-term use; Temperature cycle: -55~+125°C/20 times, temperature change rate 10°C/min, thermal stress tolerance is assessed; Constant acceleration: 20000g/Y1 direction / 1min, to evaluate the mechanical firmness. Key monitoring parameters: Visual inspection: optical microscope (50x) to observe whether there are cracks and deformations;

Mechanical properties: bond strength (tensile test) and ball shear strength (thrust test); Electrical properties: Contact resistance (four-probe method, accuracy ±1mΩ).

4.2 Test results and analysis

Comparison of performance before and after environmental test: strength retention rate: > 95% after high temperature storage and > 90% after temperature cycling, all of which meet the requirements of GJB548; Resistance variation: < maximum increment of 10mΩ, well below the failure threshold of 50mΩ; Microstructure: SEM observations show uniform growth of the IMC layer, < 1μm thick with no significant cavities. Long-term reliability prediction: Accelerated model: Based on the Arrhenius equation, the lifetime at 25°C is estimated to be > 10 years; Failure distribution: Weibull analysis shows that the shape parameter β>3, which belongs to the type of loss of consumption; Process Capability: A CPK value of 1.67 indicates excellent process stability for mass production needs.

5. Conclusion and application value

Through the systematic analysis of CMOS chip bonding failure, the following conclusions are drawn: the shelping pad is due to the insufficient bonding force of the aluminum-BPSG interface, and the "crater" is due to local stress exceeding the fracture strength of silicon, both of which are affected by multiple factors. The optimization scheme uses 25μm gold wire and a custom splitting knife to reduce the failure rate from 1.5% to 0.08% using 60mW/30ms/25g bonding parameters. This research result has been applied to an aerospace-grade CMOS chip production line, increasing the yield of the bonding process from 82% to 99.5%, saving about 6.8 million yuan in annual costs. At the same time, the established parameter optimization method can provide a reference for the bonding process of other types of chips, and has a wide range of engineering application value. Future work will focus on nanoscale bonding technology to explore reliable interconnect solutions with pitches below 0.1μm.