Four bonding methods in chip packaging

In the pyramid structure of the semiconductor industry, chip packaging plays a key role in "connecting the top and the bottom" - not only to provide physical protection for the fragile chip core (mechanical shock resistance needs to be up to 1000G acceleration), but also to achieve efficient transmission of electrical signals (latency needs to be controlled within 1ns), while also solving the problem of heat dissipation of hundreds of watts per square centimeter. As the "neural network builder" of the packaging process, the performance of bonding technology directly determines the conversion efficiency of the chip from laboratory samples to industrial products.

Contemporary bonding technology has formed a pattern of parallel technology routes: from wire bonding in the 1950s, to IBM's pioneering flip chip bonding in the 1960s, to the commercial automatic bonding of carrier tapes in the 1970s, to the hybrid bonding that has emerged in recent years, each technological breakthrough has promoted the increase in chip packaging density by 1-2 orders of magnitude. According to SEMI data in 2023, the global bonding equipment market has reached $7.8 billion, with hybrid bonding equipment growing at a compound annual growth rate of 35%, reflecting the industry's transformation trend towards high-density interconnects.

1. Wire bonding technology: the continuous evolution of the classic scheme

As the most mature interconnect technology, wire bonding still occupies more than 70% of the market share, and its core advantages are strong process compatibility (supporting a variety of wires such as gold, aluminum, and copper) and controllable equipment costs (investment of about 50-2 million yuan per equipment).

1.1 Technical principles and process systems

The technology realizes the electrical connection between the chip pad and the substrate through metal leads (diameter 15-50μm), and its process essence lies in the precise balance of "energy-time-pressure": the device needs to reach an operating temperature of 150-300°C (adjusted according to the wire), and the wire tension is controlled in the range of 0.5-5cN. Bonded wires need to be stored under inert gas protection (oxygen content < 10ppm), while copper wires require an environment with a humidity of < 30% to prevent bond failure due to oxidation. It is divided into two major schools: ball bonding and wedge bonding: ball bonding: using electrical spark (EFO) to melt the end of the wire into a gold ball with a diameter of 2-3 times the wire diameter, and press-welding it on the chip pad through thermal ultrasonic energy (temperature 180°C + ultrasonic power 50-150mW) to form the first solder joint; The second solder joint is wedge-shaped crimped, and the lead arc height is controlled at 50-150μm. Wedge bonding: No need to form a gold ball, directly use a wedge tool to press weld the wire on the aluminum pad, suitable for materials with high hardness such as aluminum wire, and the bonding strength can reach 10-20g (25μm wire diameter). Quality Control: Machine vision is used to detect solder joint diameter (deviation <10%), lead radian (angular deviation < 5°), and tensile testing (50 points per batch) to ensure strength is up to standard (gold wire > 7g, copper wire > 10g).

Technical limitations and breakthrough directions

The bottleneck of traditional wire bonding is that the minimum pin spacing is about 50μm, which is difficult to meet the needs of high-end chips with 3000+ pins, the lead inductance is about 1-5nH, which limits the transmission of high-frequency signals (>10GHz), and the thermal conductivity of the plastic packaging material is only 0.2-0.8W/m・K, which cannot meet the heat dissipation needs of high-power chips .

The industry is breaking through limitations through three innovations: 1Copper wire bonding replacement: The cost is only 1/5 of that of gold wire, and the conductivity is increased by 30%, but the oxidation problem needs to be solved (formic acid to reduce the atmosphere)2Bond Strength Enhancement: Developed Au-Ag alloy wire to increase fatigue life from 1000 temperature cycles to 3000.3Multi-wire parallel bonding technology: Achieving a bonding speed of 0.5ms per lead, which is 40% higher than the traditional one, Intel uses copper pillar lead bonding technology in its 10nm processor package to increase the bond strength to 25g, while reducing the lead inductance to 0.8nH and supporting PCIe 5.0 (32Gbps) signal transmission.

2. Flip chip bonding: the main solution for high-density interconnection

Flip chip bonding technology directly connects to the substrate through bumps on the front of the chip, realizing the innovation of "surface array interconnection" to "peripheral interconnection", and the penetration rate in high-end chips such as mobile phone processors and GPUs has reached 65%.

Process chain and technical characteristics

The complete flip bonding process consists of three core steps: Bump manufacturing Solder bumps: Pb-SN or Sn-Ag-Cu bumps (50-200μm diameter, 30-100μm height) are formed using electroplating or printing processes, and 3-5% Ag content in the solder significantly increases solder joint strength, and copper pillar bumps: copper column is plated first (20-50μm diameter) and covered with nickel/tin layer for fine pitch (<). 50μm), and the thermal conductivity reaches 401W/m・K. Chip docking: Use a high-precision placement machine (positioning accuracy ±1μm) to achieve the alignment of the bump and the substrate pad, reflow soldering process: peak temperature 240-260°C (lead-free solder), holding time 30-60 seconds, to form an intermetallic compound (IMC) layer (thickness 1-3μm). Underfilling: Epoxy injection (viscosity 500-1000cP) fills the gap between the chip and the substrate (50-100μm), curing conditions: 150°C/1 hour, ensuring the coefficient of thermal expansion (CTE) matching (difference < 5ppm/°C), which has a significant technical advantage over wire bonding: the minimum pitch can be reached 20μm, the number of pins in the same area is 5-10 times that of wire bonding, the signal path is shortened to 100-500μm, the parasitic inductance < 0.1nH, supports high-frequency signals above 100GHz, and the heat sink can be directly mounted on the back of the chip, and the thermal resistance is reduced to less than 0.5°C/W.

2.2 Technical challenges and response strategies

Core Challenges and Solutions for Flip Bonding:

TSMC uses Cu-Sn micro-bumps (15μm diameter) in a CoWoS package, combined with a high-precision flip device (alignment accuracy ±0.5μm), to achieve a density of 10,000 interconnect points per square millimeter, providing 4TB/s of memory bandwidth for the H100 GPU.

3. Automatic bonding of carrier tape: a characteristic scheme of flexible interconnection

Automatic Carrier Bonding (TAB) technology uses flexible substrates as carriers, which is especially suitable for "long" packaging needs such as LCD driver chips, and occupies more than 90% of the market share in the field of display panels.

3.1 Technical composition and technological flow

At its core, TAB technology involves attaching the chip to a flexible carrier tape (typically a polyimide substrate) of a prefabricated circuit, and the complete process includes:

1. Carrier tape manufacturing: substrate: 50-100μm thick polyimide film, covered with 18-35μm thick copper foil, circuit molding: lithography + etching to form leads (line width/spacing 20/20μm), while making positioning holes (accuracy ±1μm), surface treatment: Ni/Au (thickness 1-3μm) on the surface of the leads, to prevent oxidation

2. Inner lead bonding: chip solder joint preparation: make Au bumps (height 5-10μm) on Al pad, thermocompression bonding: temperature 300-350°C, pressure 10-30MPa, time 1-2 seconds, achieve Cu-Au interconnect detection: AOI check bond strength (>5g) and lead deformation (<10%)

3. Outer lead bonding and packaging: soldering the outer lead of the carrier tape with the PCB (temperature 220-240°C), chip area packaging: dispensing (epoxy) or film covering, forming a 100-200μm thick protective layer, according to the difference in packaging form, TAB can be divided into: TCP (Tape Carrier). Package): The carrier tape is used as a separate package together with the chip; COF (Chip On Film): Bond the chip directly to the flexible circuit of the display panel, eliminating the intermediate link

Technical advantages and disadvantages and application scenarios

The unique value of TAB technology is reflected in its ability to withstand bending deformation of ±3mm, suitable for applications such as curved screens, roll-to-roll production, 5,000 chips per hour, conventional 15/15μm line width/spacing, and advanced processes up to 10/10μmHowever, its limitations are also obvious: a complete TAB production line requires an investment of 2000-50 million yuan, far exceeding the lead bonding equipment, and the thermal conductivity of polyimide substrate is < 0.3W/m・K, which is not suitable for high-power chips, and the carrier band circuit is difficult to modify once the production is completed, and it is not suitable for small-batch customizationSamsung Display uses COF technology in its QD-OLED panel to bond the driver chip on a 0.1mm thick flexible substrate, achieving an ultra-narrow design with a bezel width of <1mm, while controlling the connection resistance below 50mΩ by optimizing the bonding temperature curve (peak 280°C, 1.5 seconds of heat preservation).

4. Hybrid bonding: a revolutionary technology for three-dimensional integration

Hybrid bonding pushes the physical limits of traditional bump interconnects through direct metal-to-metal (mainly Cu-Cu) and dielectric-dielectric (mainly SiO₂-SiO₂) bonding and is the "ultimate solution" for 3D IC packaging.

4.1 Technical principles and key processes

At its core, hybrid bonding enables close contact at the atomic level at the wafer level, with process complexity far exceeding that of traditional techniques:

(1) Surface preparation: chemical mechanical polishing (CMP): the surface roughness of copper pads and SiO₂ media should be controlled below 0.5nm (Ra value), surface activation: plasma treatment (O₂ or N₂ plasma), the introduction of hydroxyl (-OH) groups to enhance hydrophilicity, cleaning: megasonic cleaning (frequency). 1MHz) to remove particles (<0.1μm) to ensure surface cleanliness > 99.9%

(2) Low temperature pre-bonding: Alignment accuracy: use infrared alignment system to ensure deviation < 1μm(3σ), bonding conditions: apply 10-50kPa pressure at room temperature, use van der Waals force to achieve preliminary bonding, environmental control: humidity 40-50% to avoid bubbles caused by excessive surface moisture

(3) High temperature annealing: temperature curve: 300-400°C, nitrogen protection (oxygen content < 1ppm), time control: 1-2 hours, promote Cu atom diffusion and SiO₂ condensation reaction, pressure assistance: apply 100-200kPa pressure in some processes to eliminate interface voids. Compared to traditional microbump technology, hybrid bonding offers more than 100x higher interconnect density (up to 10⁶/mm²), reduced contact resistance to less than 10mΩ, and no underfill, greatly simplifying the process.

Technical challenges and industrialization progress

Commercialization of hybrid bonding faces multiple obstacles: Surface quality control: Wafer warpage is required to < 5μm or it will lead to local bond failure, CMP and alignment equipment investment is 3-5 times higher than traditional packaging, yield challenges: 12-inch wafers need to achieve 99.99% bond yield to achieve economicsCurrent progress of leading companies: TSMC: SoIC technology achieves 1μm pitch hybrid bonding with a yield of > 90% for 3D IC stacking, Samsung: plans to adopt hybrid bonding in HBM4 with a bandwidth increase of 8.19Tb/s, Intel: Foveros Direct technology achieves 2μm pitch for the next generation of Xeon processors, according to Yole's forecast, the hybrid bonding market size will exceed $5 billion in 2027, with memory (HBM) and AI chips being the main drivers.

5. Technology comparison and future evolution

Comparison of the core indicators of the four major bonding technologies:

There will be three major trends in future technological evolution:

1. Multi-technology integration: The combination of "hybrid bonding + wire bonding" is used in high-end packaging, taking into account both density and cost

2. Material innovation: develop new conductive adhesives and nano-metal solders to reduce the bonding temperature (<200°C).

3. Intelligent process: Introducing machine learning to optimize bonding parameters to achieve real-time prediction of defects (accuracy > 95%), Chinese companies are accelerating to catch up: Changdian Technology's XDFOI technology realizes hybrid bonding with 3μm line width, Tongfu Microelectronics adopts flip + lead bonding composite solution in 2.5D packaging, and Huatian Technology's COF production capacity has entered the top three in the world. With the maturity of chiplet technology, bonding technology will become a key breakthrough for China's semiconductor industry to break through the blockade.

epilogue

The evolution history of bonding technology is essentially a history of continuous optimization of the "density-performance-cost" triangle in the semiconductor industry. From the robust and reliable nature of wire bonding to the pushing boundaries of hybrid bonding, each technology plays an irreplaceable role in specific application scenarios. For industrial practitioners, technology selection needs to follow the "three-dimensional evaluation framework": the number of I/O, signal frequency, and power density determine the upper limit of technology, R&D investment, equipment depreciation, and yield loss constitute the bottom line of cost, and material availability, equipment stability, and process repeatability affect the feasibility of implementationAs Moore's Law slows down, packaging technology has risen from a "supporting role" to a "protagonist", and bonding technology, as a core link, will play a more critical role in cutting-edge fields such as chiplets and 3D ICs, promoting the semiconductor industry to enter a new stage of "More than Moore".