Three key technologies for silicon carbide power device packaging

Silicon carbide power device packaging technology breakthrough: from basic challenges to the future

Introduction: The packaging revolution triggered by wide bandgap devices

When silicon carbide (SiC) materials are subjected to bandgaps of 3.26eV (about 3 times that of silicon materials), a breakdown electric field of 2.5×10⁶V/cm (10 times that of silicon ), and 490W/m·K thermal conductivity (3 times that of silicon) and other characteristics completely break the performance ceiling of traditional power devices, packaging technology is facing unprecedented transformation pressure. This wide bandgap device, which can operate stably above 300°C and increase the switching speed by 5-10 times, pushes the efficiency target of power electronics systems to more than 99%, and the power density requirement exceeds 30kW/L

The stray inductor of traditional packaging of 10-20nH can generate voltage overshoot of up to 40% of the rated voltage at 50kV/μs dv/dt of SiC devices, far exceeding the device safety threshold, and the packaging material system suitable for silicon devices (such as traditional solder) softens significantly above 150°C, resulting in the power cycle life of the module plummeting from 10⁵ times to less than 10⁴ times in the 200°C operating environment. The flat layout of discrete components makes it difficult to exceed 100mm² of converter loop area to meet the needs of high-density integration

These contradictions are driving a paradigm shift in packaging technology from "compatible silicon devices" to "exclusive SiC optimization". According to Yole Development, the global SiC power device packaging market size reached $1.28 billion in 2023, of which the proportion of products using advanced packaging technology jumped from 15% in 2018 to 42%, and this proportion is expected to exceed 70% in 2028. This paper systematically analyzes the three key technological breakthrough directions of SiC packaging, and provides the industry with a reference for the whole chain from the laboratory to the production line by comparing the technical characteristics and industrialization prospects of various solutions.

1. Low stray inductive packaging: the core breakthrough of electrical performance

The "aerial loop" formed by the metal bonded wires in conventional packaging and the flat layout of the lead frame make the converter path like a winding river, and the stray inductance remains high. The high-frequency nature of SiC devices amplifies this problem into a systemic risk - a 1200V/100A SiC module overshoots up to 600V during switching at 20nH stray inductance, which directly leads to avalanche failure of the device. The core of solving this problem is to reconstruct the current path and realize the layout innovation of "linear, flat, and layered".

1.1 Bonding wire substitution technology: from point contact to face contact

Metal-bonded wires (25-50μm in diameter) serve as the "bottleneck" for current transmission, accounting for more than 60% of the total stray inductance. The alternative presents a multi-technology path: Infineon's Hybrid Pack module uses a 0.2 mm thick copper clip for front-to-chip connection, reducing the current path to 1/5 of the bond wire solution through face contact, and reducing stray inductance from 15 nH to less than 5 nH. This technology demonstrates excellent consistency across 1200V/200A modules, with batch-to-batch inductance deviations of <3%.

Silicon Power has developed a patented technology that solder copper terminals directly to the chip pad with a specially designed lead frame to control the stray inductance of 1200V/300A SiC JFET modules at 4nH, which is 70% lower than traditional bondwire solutions. Temperature cycling tests (-40°C~150°C) show that the solder joint reliability is 3 times higher than that of aluminum bonded wires. Semikron's SKiN packaging technology uses a flexible PCB on a polyimide substrate instead of a bonding wire, and the via formed by laser drilling is used to achieve interlayer connection, and the stray inductance of the 1200V/400A module is only 1.5nH, reducing switching losses by 50% compared to traditional modules. The key to this technology is the machining accuracy control of 0.1mm ultra-fine vias, and the position deviation needs to be <±20μm. The common feature of these technologies is the shift from "multiple thin wires in parallel" to "integral surface contact", which not only reduces inductance, but also increases the current carrying capacity by 3-5 times, which is especially suitable for high-current applications in SiC devices.

1.2 Three-dimensional layout technology: inductance offset in three-dimensional space

The stacked structure realizes mutual cancellation of inductance by reverse parallelism in the current direction, which is especially effective in high-voltage modules:

The innovative structure proposed by the CPES team arranges the power loop of the DBC substrate in layers with the drive loop of the PCB, and realizes vertical interconnection through a 200μm diameter via. The measured stray inductance of the 1200V/100A half-bridge module is 3.8nH, which is 65% lower than the traditional flat layout. The solution is only 60% of the volume of traditional modules, and the power density exceeds 20kW/L. The 3D structure developed by the University of Grenoble-Alpes stacks the lower tube chip directly on top of the upper tube, reducing the wiring length at the midpoint of the bridge arm from 10mm to 0.5mm and reducing stray inductance to less than 1nH. Experimental data show that the common-mode current of this structure is reduced by 80% compared with traditional modules, and EMI interference is significantly improved. CRRC Times Electric's 10kV SiC modules feature a spring-loaded crimp structure that achieves long-term reliable contact through elastic compensation by molybdenum-copper composites. The module's stray inductance is < 5nH and the contact resistance change rate is < 10% after 1000 thermal cycles, making it particularly suitable for high-voltage DC transmission scenarios.

The challenge of three-dimensional layout technology lies in thermal stress management, and the difference in thermal expansion coefficients of different materials may lead to separation between layers. A simulation analysis shows that the combination of Si₃N₄ ceramic (CTE 3.0 ppm/K) and Cu/Mo alloy (CTE 6.8 ppm/K) can reduce the interlayer stress to less than 70 MPa to meet the long-term reliability requirements.

1.3 New packaging structure: from discrete to system-level integration

Breaking through the shell limitations of traditional packaging and realizing the collaborative design of chips and peripheral components is the ultimate solution to reduce system-level inductance:

The SiC chip is embedded in the positioning slot of the ceramic substrate and the electrode interconnect is achieved by sputtering a metal layer, eliminating the lead-frame inductance of traditional packaging. This technology maintains stable performance at temperatures of 279°C, making it suitable for extreme environments such as aerospace. Soldering porcelain sheet capacitors directly inside the power module reduces the distance from the capacitor to the chip from 50mm to 5mm and reduces loop inductance by 90%. An integrated module developed by Zhejiang University shows that this structure reduces the switching oscillation amplitude from 20% to less than 5%.

Wolfspeed's CSP-type SiC MOSFETs connect directly to the PCB via a solder joint array, eliminating the pin structure of traditional packages, with a parasitic inductance of only 0.5nH and a switching speed of 100kV/μs, making them ideal for high-frequency power supplies.

These innovative structures transform the package from a "device container" to a "performance enhancer," providing the best stage for SiC devices to be featured.

2. High-temperature packaging technology: reconstruction of material system

SiC chips can work stably above 300°C, but traditional packaging materials have a performance inflection point at 150°C - solder softening leads to an increase in contact resistance, plastic degradation to produce gas, and cracks between ceramic substrates and metal layers due to thermal mismatch. The core of high-temperature packaging technology is to build a full-chain high-temperature resistant material system from chips to heat sinks, forming a three-dimensional synergy of "material-process-structure".

2.1 Chip Connection Materials: From Solder to Sintering

The chip-to-substrate connection layer is a dual channel for heat export and current transfer, and its high-temperature performance determines the upper operating temperature of the module: Au80Sn20 eutectic solder (melting point 280°C) has a shear strength retention rate of 80% at 200°C, which is much higher than SAC305 solder (50%). However, the cost of 1500 yuan/kg makes it only used in high-end fields such as aerospace, and the solder void rate needs to be controlled at <5%, otherwise it will lead to local overheating. Nano silver paste (particle size 20-50nm) is sintered at 250°C/5MPa to form a silver layer with a density of > 85%, and the thermal conductivity is 200W/m·K, which is 4 times that of conventional solder. The pressureless sintering process developed by Tianjin University achieves low-temperature sintering (200°C) by adding organic binders, so that the power cycle life of the 1200V/100A module at 300°C reaches 10⁴ times, which is 5 times that of the soldering solution . Cu-Sn alloys form a liquid phase at 260°C and cool to form Cu₃Sn intermetallic compounds with high melting points that can operate at temperatures up to 300°C. The advantage of this technology is that it has good process compatibility and can continue to use existing solder printing equipment at only 1/3 the cost of sintered silver.

Material selection requires a balance between performance and cost: automotive-grade modules are mostly sintered silver to meet the 15-year/150,000-kilometer life requirements, while industrial-grade applications can be controlled by TLB technology.

2.2 Substrate material: a key node in thermal management

As a bridge connecting the chip and the heat sink, the performance of the substrate needs to meet the "three high" requirements - high thermal conductivity, high dielectric strength, and a thermal expansion coefficient that matches the chip: thermal conductivity 170W/m・K (Al₂O₃). 4 times that of SiC), and CTE 4.5ppm/K (close to SiC's 3.7ppm/K), making it an ideal high-temperature substrate material. When a 1200V/200A module uses an AlN substrate, the thermal resistance of the shell drops from 0.3°C/W to 0.15°C/W, allowing the chip junction temperature to be increased by 50°C. However, it costs three times more than Al₂O₃, limiting large-scale adoption. With flexural strength of up to 900MPa (twice that of Al₂O₃) and a CTE of 3.0ppm/K (best matched with SiC), it exhibits exceptional reliability over temperature cycling. However, the thermal conductivity is only 70W/m・K, and it is necessary to use it with a high thermal conductivity interface material. Through the direct bonding of copper to ceramics, the thermal resistance of the oxide layer of traditional DBC substrates is eliminated, resulting in a 20% increase in overall thermal conductivity. CRRC Times Electric's 10kV module uses AMB-AlN substrate to successfully control the chip junction temperature below 175°C.

The decision tree of substrate selection shows that AlN-AMB substrate is the optimal choice when the power density is > 20kW/L; For cost-sensitive low- to medium-power applications, Al₂O₃ substrates remain competitive.

2.3 Encapsulation and potting material: the last barrier of system protection

Insulation and protection in high-temperature environments require new material system support: using Cu/W alloy (CTE 6.5ppm/K) to replace the traditional copper shell, reducing the thermal mismatch stress with the ceramic substrate by 50%, and there is no risk of cracking in the -55°C~200°C cycle. The silicone rubber-based potting material maintains a volumetric resistivity of > 10¹⁴Ω cm at 200°C, a breakdown field strength of > 20kV/mm, and a wide operating temperature range of -60°C~250°C, making it ideal for high-temperature modules. Polyimide coatings can maintain good dielectric properties at 300°C and can be used for secondary protection on the chip surface to prevent ion migration at high temperatures. The combination of these materials allows the insulation resistance of SiC modules to maintain > 10¹¹Ω at 250°C, meeting high-temperature insulation standards such as UL 1557.

3. Multi-functional integrated packaging: the ultimate pursuit of power density

The miniaturization of SiC devices makes it possible to integrate packages, integrating functions such as drive, protection, and sensing into the module, which can reduce the size of the system by more than 50% while further reducing parasitic parameters. This "modular system" concept is reshaping the design paradigm of power electronics.

3.1 Drive circuit integration: the key to reducing latency

Traditional discrete drivers do not realize the high frequency potential of SiC devices due to signal delays (typically 50-100ns) due to long leads. The integration solution presents three stages of development: connecting the driver chip and the power module through a flexible PCB, shortening the drive loop length to less than 10mm and reducing the latency to less than 20ns. Mitsubishi's SiC-IPM modules use this structure to increase the switching frequency to 200kHz, which is 1x higher than the separation solution. The drive circuit is directly fabricated in the edge area of the power substrate, and the PCB process is used to realize the hierarchical layout of the gate driver and the power loop. The 1200V half-bridge module developed by Zhejiang University integrates the drive circuit, and the overall volume is only twice that of the TO-247 single tube, and the drive loop inductance is < 1nH. The driver chip is made using the SiC CMOS process, and the monolithic integration with the power device is realized, completely eliminating parasitic parameters. Research from the University of Arkansas shows that this structure can reduce drive latency to 5 ns and reduce switching losses by another 15 percent. The challenge of integrated drivers is isolation and heat dissipation - SOI driver chips can achieve isolation voltages of more than 4kV, while arranging the driver circuit at the edge of the substrate with better heat dissipation can control the driver chip temperature below 125°C.

3.2 Passive Component Integration: The Core of System-Level Optimization

Close integration of passive components such as capacitors and inductors with power devices can significantly reduce system-level parasitic parameters: soldering porcelain capacitors (X7R media) inside the module close to the chip reduces the power loop area from 1000mm² to 100mm² and reduces stray inductance by 90%. Test data shows that this structure reduces the switching voltage overshoot from 40% to less than 10%. A common-mode inductor is embedded in the module housing to suppress EMI using the high-frequency properties of the core material. This design of a 5G power module reduces radiated disturbance by 20dB in the 10MHz-1GHz band and meets the EN 55022 standard without the need for additional filters. Temperature and current sensors (such as Hall components and RTDs) are implanted near the chip to achieve real-time status monitoring. Infineon's Hybrid Pack Drive module improves system safety by reducing the response time for over-temperature protection from 10ms to 1ms by integrating a temperature sensor.

Passive integration requires a balance between volume and performance – 1μF capacitance can be achieved in a 0.5cm³ volume with laminated ceramic capacitors (MLCCs), while planar inductors can provide 10μH in the same volume to meet the needs of most high-frequency applications.

3.3 Advanced heat dissipation technology: break through the bottleneck of thermal resistance

The high power density of SiC devices (>300W/cm²) makes heat dissipation the biggest challenge for integrated packaging, and traditional air cooling (10-50W/m²・K) can no longer meet the demand, so a more efficient cooling solution must be adopted: 0.2-0.5mm wide microchannels are made inside the substrate, and water-glycol coolant (flow rate 1-2L/min) can achieve 10,000-50,000W/m² ・K heat transfer coefficient. A 1200V/400A module uses this technology to reduce the thermal resistance of the enclosure to 0.08°C/W, which is 75% lower than conventional air cooling. The upper and lower surfaces are made of DBC substrate and microchannel cold plate at the same time, which increases the heat dissipation area by 1 times. CRRC Times Electric's double-sided cooling module shows that at the same power, the chip junction temperature is reduced by 30°C compared to single-sided heat dissipation, and the power cycle life is extended to 2 times. The phase transition of the working fluid is used to absorb a large amount of latent heat (such as the latent heat of the phase change of fluoride liquid > 100kJ/kg), and the heat is quickly exported with the heat pipe. This technology is particularly suitable for space-constrained situations, such as electric vehicle inverters, which can achieve a cooling capacity of 100kW in a 3L volume. The innovation direction of heat dissipation technology is "zero-distance contact" - microchannels are made directly on the chip substrate, and the thermal resistance can be reduced to less than 0.05°C/W, but this needs to solve the insulation problem between the chip and the heat sink, and beryllium oxide (BeO) coating is a potential solution due to its high thermal conductivity of 280W/m·K.

4. Challenges and prospects: the leap from laboratory to mass production

While SiC packaging technology is rapidly evolving, it still faces multiple challenges that also breed new technological opportunities: sintered silver materials are 10 times more expensive than traditional solder, and AMB substrates are 5 times more expensive than DBC, limiting the adoption of SiC modules. Solutions include: developing micron silver powder to reduce the cost of sintering materials; Optimize the AMB process to improve yield; Low-cost alternative technologies such as copper clips are used. The cost per unit power of advanced packaging is expected to decline by 50% by 2025, on par with silicon devices. The long-term reliability data of SiC modules at high temperatures (>200°C) are insufficient, especially the growth pattern of intermetallic compounds (IMCs) is still unclear. It is necessary to establish a new accelerated aging model to extend the traditional 150°C/1000-hour test to 250°C/5000-hour, and develop in-situ monitoring technology to observe interface evolution in real time. The packaging form of different manufacturers is very different.