Panoramic analysis of packaging substrate technology and exploration of industrial development path

Introduction: The strategic position of packaging substrates

In the semiconductor industry chain, packaging substrates are the key connection hubs between chips and PCBs, and their technical level directly restricts the high-density integration and system-in-package (SiP) process of integrated circuits. With the mass production of 3nm process chips and the maturity of chiplet technology, packaging substrates are upgrading from traditional "electrical interconnect carriers" to "system integration platforms", which undertake multiple functions such as signal transmission optimization, thermal management regulation, and mechanical support. According to Prismark's 2023 report, the global packaging substrate market has exceeded $12 billion, with high-end products used in 5G base stations and autonomous driving chips growing at an annual growth rate of 18%, becoming a new engine for the growth of the semiconductor industry.

1. The core technology system of packaging substrates

1.1 Functional positioning and classification architecture

The technological evolution of packaging substrates has always revolved around the core goal of "increasing interconnect density", and its three core functions are differentiated in different application scenarios: Physical support and thermal management: In high-power device packaging, the substrate needs to have 1.5W/(m・).K) and above, such as the AlN ceramic substrate used in automotive-grade IGBT modules, can control the chip junction temperature below 125°C. Electrical interconnect bridges: In high-frequency scenarios (such as millimeter-wave radar), the dielectric loss (Df) of the substrate needs to be ≤0.002@10GHz to reduce signal transmission attenuation. System Integration Platform: By embedding passive components (resistors, capacitors), the substrate can reduce the module size by 30%, typical applications such as SiP packaging for Apple's M1 Pro chip.

Based on the classification system of the IEEE 2865 standard, combined with the cross-analysis of connection technology and application scenarios, a more detailed classification matrix can be constructed:

1.2 Flip Chip technology innovation

Flip soldering technology realizes the direct interconnection between the chip and the substrate through copper pillar bumps, which brings revolutionary improvements over traditional wire bonding: Density breakthrough: The use of 40μm pitch copper pillar bumps can achieve an I/O density of 1000+ per square millimeter, which is 5 times higher than WB technology, meeting the high-end chip needs of 3000+ pins. The 10μm copper pillar process used in TSMC's CoWoS packaging pushes interconnect density to a new level. Performance Jump: The signal transmission path is shortened from a few millimeters in the WB to tens of microns in the FC, parasitic inductance is reduced by more than 60%, and signal integrity is improved by 30% at 10GHz high frequencies. The JEDEC JESD22-B104 impact test shows that the FC structure has a mechanical impact resistance of up to 1500G, which is 2.5 times that of the WB structure. Thermal resistance optimization: The thermal conduction efficiency of copper pillar bumps (398W/(m・K)) is much higher than that of gold wire (317W/(m・K)), and with the heat dissipation through-hole design, the thermal resistance of the chip can be reduced by 40%, especially suitable for high-power chips above 300W.

2. Breakthroughs in manufacturing technology and material technology

2.1 Ultra-precision manufacturing process bottlenecks

The manufacturing of high-end packaging substrates has entered the era of "micron-level competition", and its process complexity is comparable to that of semiconductor wafer processing. The technical indicators of "three highs and two smalls" (high multi-layer, high density, high reliability, small line width, small through-hole) put forward the ultimate requirements for processing equipment:

Line processing: Laser direct imaging (LDI) technology is used with negative photoresist to achieve stable mass production of 5μm line width/line spacing. ASML's NXE series lithography machine modification model has a line width control accuracy of up to ±0.5μm to meet the needs of 7nm chip packaging. Through-hole molding: UV laser drilling technology can process micro-throughs with a diameter of 15μm, with hole position accuracy controlled within ±3μm. Compared to conventional mechanical drilling, the efficiency is 8 times higher and there is no burr residue problem. Interlayer alignment: Adopting a dual-camera vision alignment system with nanoscale scales, the interlayer alignment tolerance can be controlled at ±3μm, ensuring the reliability of interconnection for stacked structures above 16 layers.

Compared with traditional HDI PCBs, the process accuracy requirements for packaging substrates are increased by an order of magnitude:

2.2 Technical game of material system

The selection of materials for packaging substrates needs to find a balance between electrical properties, thermal stability, and processability, forming a competitive landscape of two mainstream technical routes: ABF and BT resin:

ABF (Ajinomoto Build-up Film) material system

Dielectric Properties: Dielectric constant (Dk) 2.9-3.3 and dielectric loss (Df) 0.002-0.004 at 10GHz frequency, suitable for high-speed signal transmission. Thermomechanical properties: The glass transition temperature (Tg) ≥ 180°C, and the coefficient of thermal expansion (CTE) above Tg is 50ppm/°C, which can be reduced to 35ppm/°C by adding SiO₂ packing. Process Adaptability: Suitable for photosensitive imaging processes, it can achieve fine line processing below 10μm, and is widely used in FC-BGA substrates with more than 16 layers. Samsung's latest HBM package features ABF material for stable interconnection of 8 channels of memory.

BT (Bismaleimide Triazine) resin system

Thermal stability: Tg value can reach more than 220°C, thermal weight loss rate at 150°C < 0.5%/1000h, suitable for automotive-grade high-temperature environments. Mechanical properties: bending strength ≥ 150MPa, interlaminar peel strength ≥0.8kN/m, mechanical reliability better than ABF material. Cost advantage: Compared with ABF materials, BT resin has a 20-30% lower raw material cost and is widely used in consumer electronics, such as the RF module substrate of Huawei Mate series mobile phones.

Exploration of emerging materials

Low-temperature co-fired ceramics (LTCC): With dielectric constants as low as 5.0 and thermal conductivity of up to 3W/(m・K), they excel in mmWave AiP antenna packages and are used in Apple's iPhone 14's 5G antenna modules. Glass substrate: Using high-purity glass doped with B₂O₃, with a surface roughness of Ra≤0.5nm, it can reduce transmission loss to 0.2dB/cm, making it a potential choice for future terahertz communication.

3. Global market pattern and localization breakthrough

3.1 Analysis of market competition situation

The global packaging substrate market presents a highly concentrated competitive landscape, and leading companies dominate with technical barriers and scale effects:

1. The first echelon: Japan's Ibiden (23% market share), Taiwan's Unimicron (19%), and South Korea's SEMCO (20%), controlling a total of 62% of the high-end market share. These companies have fine wire processing capabilities below 10μm and mainly supply chip giants such as Intel and Samsung.

2. The second echelon: Taiwan's Xinxing Electronics (12%), Japan's Panasonic (8%), focusing on the mid-to-high-end market, with technical indicators covering the 15-25μm line width range.

3. Chinese mainland enterprises: Shennan Circuit (3.2%), Zhuhai Yueya (2.1%), Xingsen Express (1.5%), mainly concentrated in the low-end field with a line width of more than 25μm, and gradually breaking through in automotive electronics and other market segments.

The generation gap in technology is the main gap faced by domestic manufacturers: international leaders have achieved mass production of 8μm line widths, while the main products of domestic companies are still at the level of 20-25μm, and the dependence on imports of equipment (Fujikura's laser drilling machine in Japan accounts for 70% of the domestic market) is an important constraint.

3.2 The "three-step" strategy for localization breakthroughs

Based on the domestic industrial base and market demand, the localization of packaging substrates needs to adopt a gradual breakthrough strategy:

Step 1: Capacity Building (2023-2025) Focus on building FC-CSP substrate production capacity, aiming to reach 100,000 square meters/month by 2025 to meet the packaging needs of domestic smartphone APs and RF chips. Breaking through the 20μm line width processing process, the yield is increased to more than 90%, and the unit cost is reduced to less than 1.2 times the international level. The localization rate of equipment has reached 50%, focusing on breakthroughs in key equipment such as laser direct imaging machines and vacuum laminators.

Step 2: Technical Tackling (2025-2027)

Tackle ultra-fine line technology below 10μm, develop supporting ultra-thin copper foil (3μm) and high-performance photoresist, and establish an independent material system. Master the design of stacked structures with more than 12 layers, develop embedded resistor/capacitor technology, and increase substrate integration by 40%. Achieved a breakthrough in the field of automotive-grade BT substrates, passed AEC-Q200 certification, and entered the supply chain of Tesla and BYD.

Step 3: Ecological Collaboration (2027-2030)

It has jointly established a joint laboratory with packaging and testing companies such as Changdian Technology and Tongfu Microelectronics to develop special substrates for chiplets and support heterogeneous integration of 1000+I/O. Build an "equipment-material-design-manufacturing" industry alliance, such as the advanced packaging substrate platform developed by CLP 58 in cooperation with Huawei HiSilicon. The global market share has increased to 15%, and import substitution has been achieved in high-end fields such as 5G base stations and AI chips.

4. Future technology trends and application expansion

4.1 Chiplet-driven technological change

The maturity of heterogeneous integration technology is driving the evolution of packaging substrates in the direction of "ultra-large size, ultra-high layer count, and super function":

Area breakthrough: Expands the size of a single substrate from the traditional 800mm² to 1200mm², supporting side-by-side integration of multiple chiplets. AMD MI300X features a 12-layer substrate with an area of 1100mm² and 13 chiplets integrated. Layer number jump: From the current mainstream 12 layers to 16 or even 20 layers, the interlayer interconnection adopts "laser blind hole + copper column" hybrid technology, and the through-hole density is increased to 1000/cm². Functional integration: Embedded silicon interposer enables 2.5D interconnection with a signal transmission rate of 112Gbps PAM4, which is 3 times faster than traditional gold wire bonding. TSMC's CoWoS package has enabled the co-design of silicon bridges and substrates.

4.2 Reliability standard system construction

With the expansion of application scenarios, the reliability testing standards of packaging substrates are becoming more and more perfect, mainly including:

Temperature cycling test: Following JEDEC JESD22-A104 condition B (-55°C~125°C, 1000 cycles), the number of solder joint failures is < 1%, and the IMC layer thickness is increased by < 2μm. Damp heat aging test: According to IPC-9701 standard, 85°C/85% RH environment for 1000 hours, insulation resistance retention rate > 90%, no electrochemical migration phenomenon. Mechanical reliability test: After vibration test (20-2000Hz, 196m/s²), the resistance change rate is < 5%; After drop test (1.5m height), there are no structural cracks.

4.3 Expansion of emerging application scenarios

Vehicle Radar: 77GHz millimeter-wave radar with LTCC substrate, which can achieve angular resolution of 0.1°, and the dielectric constant stability of the substrate in -40°C~125°C environment <±0.1. Quantum computing: Developing ultra-low loss (<0.1dB/cm) superconducting substrates to support qubit interconnects in 4K low-temperature environments, IBM quantum computers have adopted customized packaging substrates. Flexible electronics: PI-based flexible packaging substrates that can withstand 100,000 bends (5mm radius of curvature) for biosensor packaging in wearable devices.

epilogue

As a key link in the semiconductor industry chain, the technical level of packaging substrate directly determines the system integration capability of integrated circuits. In the face of global technological competition and domestic demand upgrades, domestic manufacturers need to achieve collaborative breakthroughs in material systems, manufacturing equipment, design tools, etc. In the next five years, with the popularization of chiplet technology and the release of advanced packaging capacity, packaging substrates will usher in a strategic transformation from "following innovation" to "leading development", providing core support for the independent and controllable of China's semiconductor industry.