Four bonding methods in chip packaging

The four major bonding technologies for chip packaging: the evolution from tradition to the future

In the precision manufacturing chain of the semiconductor industry, chip packaging plays a dual role as a "protector" and a "connector" – it not only provides a physical barrier for fragile bare chips, insulating external moisture, dust, and mechanical shocks, but also plays a key role in electrical signal transmission and heat dissipation. As the core process of the packaging process, bonding technology is like building a "bridge" for chips to communicate with the outside world, which directly determines the performance, reliability and miniaturization level of integrated circuits. At present, there are four main types of bonding technologies that are maturely applied in the industry: wire bonding that has been tested for more than half a century, flip chip bonding that promotes high-density packaging, automatic carrier tape bonding that realizes automated mass production, and hybrid bonding that leads 3D integration. These technologies have their own focuses and together support the full range of applications from consumer electronics to aerospace and military industry.

1. Wire bonding: the "evergreen" of the encapsulated world

Since its birth in the 50s of the 20th century, wire bonding technology is still the most widely used bonding method due to its mature process and cost-controllable advantages. The core principle is to connect the pads on the chip surface to the corresponding pads on the substrate (lead frame or PCB) using metal leads (typically 15-50 μm in diameter) to achieve a reliable connection between metals using heat, pressure, or ultrasonic energy. This technology is like using "nanowires" to build external circuits for chips, and although it may seem traditional, it can adapt to a variety of chip types and packaging formats.

1. Process characteristics and limitations

Wire bonding has clear requirements for chip design: pads must be distributed along the edges around the chip to form a "peripheral routing" structure. The presence of metal leads requires a certain amount of space in the package, which is gradually becoming a bottleneck in today's pursuit of miniaturization - in the case of mobile phone processors, the package area with wire bonding is usually more than 30% larger than the flip chip solution. At the same time, the wrapping structure of the lead and the plastic body can hinder heat conduction, causing the chip operating temperature to increase by 5-10°C, affecting high-frequency performance.

Despite its limitations, wire bonding still dominates the low-to-mid-end chip segment. According to data from a research institution, 70% of the world's integrated circuit packages in 2024 will still use wire bonding technology, especially in power management chips, RF devices and other fields.

2. Technical branches and application scenarios

Depending on the bonding morphology and energy source, wire bonding can be divided into several technical branches:

Spherical bonding and wedge bonding: Spherical bonding (ball welding) melts the top of the wire into a ball through electrical sparks, and then press-welds it to the chip pad, which is suitable for materials with good ductility such as gold wire; Wedge bonding (wedge welding) is directly press-welded with metal wire, which is more suitable for wires with higher hardness such as aluminum wire. The solder joint strength of ball welding can reach 15-20g, while wedge welding can reach 20-30g, adapting to different mechanical reliability requirements.

Thermocompression Bonding (TCB): Connecting at 150-300°C and 10-200MPa pressure, the TCB process jointly developed by Intel and ASMPT reduces the I/O pitch to 10μm, and has become the mainstream solution for high-end wire bonding since mass production in 2014. The innovation is to only heat the chip side to avoid the warping problem caused by the overall heating of the substrate, and data from a fab shows that the warpage of the substrate is reduced from 50μm to less than 10μm after using TCB technology.

Ultrasonic and thermal ultrasonic bonding: Ultrasonic bonding uses ultrasonic vibration at 20-60kHz to generate frictional heat, which can be operated at room temperature, especially suitable for temperature-sensitive chips; Thermal ultrasonic bonding combines temperature, pressure and ultrasonic energy, and the bond strength is 40% higher than that of thermocompression bonding alone, and is widely used in automotive electronics and other fields with high reliability requirements.

It is worth noting that with the trend of copper leads replacing gold wires, bonding technology is also continuing to innovate. Kulifax's flux-free bonding technology, introduced in 2023, enables copper-copper bonding in nitrogen or argon environments, solving the problem that traditional fluxes are difficult to clear at fine pitches (<10μm), increasing bond yield from 85% to 99%.

2. Flip chip bonding: the "main force" of high-density packaging

Flip chip bonding technology, pioneered by IBM in the 1960s, revolutionized the way chips are connected to the substrate - it directly connects the chip to the substrate pad through an array of metal bumps (Bumps) with the chip facing down, just like "upside down" on the substrate, so it is also known as flip bonding. This area array interconnect method breaks the peripheral wiring limitations of wire bonding and becomes the core technology of high-performance chip packaging.

1. Performance advantages and process characteristics

The advantages of flip chip bonding are reflected in multiple dimensions: Density and speed: With rerouting (RDL) technology, the number of I/O per unit area is 5-10 times that of wire bonding, and millions of I/O can be achieved on 300mm wafers. The signal transmission path is shortened to 100-500μm, which is more than 80% less than wire bonding, and the signal integrity is significantly improved, making it suitable for high-frequency scenarios such as 5G base stations and AI chips. The back of the chip can be directly in contact with the heatsink, and the thermal resistance is reduced to 0.5-1°C/W, which is 60% lower than the plastic wire bonding solution, and the full load temperature of the chip is reduced from 95°C to 75°C after a GPU vendor uses flip chips. The reflow soldering process can process hundreds of chips at the same time, and the 28nm chip production line of a packaging factory has a single-furnace flip bonding capacity of 500 pieces/hour, which is more than 10 times that of wire bonding.

2. Technical challenges and solutions

The main problem of flip chips lies in thermal mismatch and solder joint reliability: the difference in the thermal expansion coefficient of the chip (silicon, CTE 2.6ppm/°C), substrate (organic material, CTE 15-20ppm/°C) and solder ball (tin-lead alloy, CTE 25ppm/°C) will generate stress during the temperature cycle, resulting in cracking of the solder joint. The solution includes: Underfill technology: injecting epoxy resin into the gap between the chip and the substrate, filling around all solder joints through capillary action, forming an elastic buffer layer after curing, reducing solder joint stress by 70%, and after 1000 cycles of -55°C to 125°C, the solder joint integrity rate of an automotive-grade chip was increased from 60% to 98% after 1000 cycles of -55°C to 125°C.

Bump structure optimization: The use of copper pillar bumps (Cu Pillar) instead of traditional weld balls, the height is increased from 50μm to 150μm, which can absorb more thermal stress; A nickel barrier layer (Ni UBM) is added to prevent metal cross-diffusion and extend solder joint life by more than 3 times.

At present, flip chip bonding has become the standard configuration of high-end processors, FPGAs and other products, and advanced packaging platforms such as TSMC's CoWoS and Intel's EMIB are based on flip technology to support the continuous improvement of chip performance.

3. Automatic bonding of carrier tapes: "experts" in flexible connections

Carrier Tape Auto-Bonding (TAB) technology combines chips with flexible carrier tapes, pioneering a new "chip-carrier-substrate" connection model. This bonding method with polyimide (PI) carrier as the carrier is especially suitable for scenarios with a large number of leads and small spacing, and occupies an almost monopoly position in the field of display driver chips.

1. Technical architecture and process innovation

At the heart of TAB technology is a prefabricated carrier tape – copper foil is applied to the PI film, photo-etched to form fine wires (line width/spacing up to 20/20 μm), and positioning holes and lead windows are reserved. The process includes: Internal Lead Bonding (ILB): Connecting chip pads to in-carrier leads in batches by thermocompression or thermoultrasonic can complete the bonding of hundreds of wires at a time, which is 5-8 times more efficient than wire bonding. Outer Lead Bonding (OLB): Connect the outer lead of the carrier tape to the PCB or display panel, often using hot-press soldering to create a stable electrical path. If only the internal lead bonding is performed, it forms a TCP (Tape Carrier Package) or COF (Chip On Film) package, which is widely used in driver chips for LCD/OLED panels. According to data from a display module factory, the number of pins in the COF package can reach more than 2,000, which is 20 times that of traditional wire bonding, which perfectly meets the signal transmission needs of ultra-high-resolution screens.

2. Advantages and disadvantages and application boundaries

The advantages of TAB technology are significant: high automation (yield up to 99.5%), excellent electrical performance (lead inductor < 1nH), and suitable for high-volume production. However, there are also obvious limitations: cost and flexibility: the lithography mask cost of customized carrier tapes is as high as hundreds of thousands of yuan, and the replacement product needs to redesign the carrier tape, which is only suitable for products with an annual production capacity of more than one million. Reliability Challenge: CTE mismatch between the PI carrier tape and the chip can lead to fatigue breakage, which is 3-5 times higher than that of flip chips in temperature cycling tests. It is difficult to rework after bonding, and the repair rate data of a mobile phone screen factory shows that the repair cost of TAB packaging is more than 10 times that of wire bonding.

Therefore, TAB technology is mainly concentrated in specific fields such as display drivers and printer control chips, and the global market size will be about $12 billion in 2024, accounting for about 8% of the total chip packaging.

4. Hybrid bonding: the "future engine" of 3D integration

When the bump spacing of flip chips struggles to exceed 1μm, hybrid bonding technology comes into play. This innovative solution that combines metal bonding (Cu-Cu direct bonding) with dielectric bonding (SiO₂-SiO₂ bonding) eliminates the need for traditional bump structures and enables sub-micron interconnects, becoming the core technology for 3D IC integration with chiplets.

1. Technical principles and breakthroughs

The hybrid bonding process exemplifies the ultimate in precision manufacturing: Surface pretreatment: Chemical-mechanical polishing (CMP) controls the wafer surface roughness below 0.1nm, and then plasma activates it to form a hydrophilic surface, laying the foundation for bonding.

Room temperature pre-bonding: The two wafers are bonded at room temperature, and the hydrogen bonding between SiO₂ molecules makes them initially bond, at which point there is a small gap between the copper contacts. Heated at 300-400°C, copper atoms form metallurgical bonds through diffusion, while SiO₂ further reacts to achieve permanent bonding, and the final bond strength can reach more than 200MPa. The technology's incredible interconnect density – Samsung HBM4 uses hybrid bonding to reduce the I/O pitch to 0.4μm, enabling 1 million interconnect points per square millimeter, which is 1,000 times faster than traditional microbump technology.

2. Performance advantages and industrialization challenges

The benefits of hybrid bonding are reflected in multiple dimensions: Electrical performance: Copper direct bonding reduces resistance by 50% and inductance by 80% compared to sold-ball interconnects, and an AI chip uses hybrid bonding to increase data transfer rates from 28Gbps to 112Gbps.

Heat dissipation and strength: The thermal conductivity of metal-dielectric composite structure reaches 150W/(m・K), which is 3 times higher than that of flip chips. Mechanical strength is strong enough to support wafer stacks over 12 layers, laying the foundation for 3D storage. Process simplification: 40% reduction in process flow compared to microbump technology, data from one fab shows a 25% reduction in HBM packaging costs. However, industrialization still faces multiple challenges: strict surface flatness requirements (global flatness < 50nm), bond alignment accuracy needs to be controlled within 0.1μm, and equipment investment is 5-8 times higher than traditional bonding. At present, major manufacturers such as TSMC and Samsung have achieved initial mass production, and it is expected that the penetration rate of hybrid bonding in high-end packaging will exceed 20% in 2026.

5. Technological evolution and scenario adaptation

The development paths of the four bonding technologies show obvious complementarity:

Wire bonding: Maintain cost advantages in low and medium I/O density scenarios, and continue to upgrade technologies such as copper wire replacement and flux-free, and are expected to occupy more than 50% of the market share in the next 5 years. Flip chip: As the mainstream solution of high-performance packaging, it is irreplaceable in mobile processors and server chips, and will continue to support the increase in I/O density as the number of RDL layers increases (reaching 8 layers).

TAB technology: Maintaining a monopoly in segments such as display drives, innovations in flexible carrier materials such as PI / metal composite tapes will further enhance their reliability. Hybrid bonding: Becoming the core engine of 3D integration, applications such as HBM4 and Chiplet will drive its rapid maturity and are expected to dominate the high-end packaging market by 2030.

Choosing the right bonding technology requires a combination of chip type, number of I/O, performance requirements, and cost budget – not only a technical decision, but also a business strategy. In today's semiconductor industry's pursuit of "More than Moore", the innovation of bonding technology will continue to break through the physical limits and provide solid support for the performance leap of integrated circuits.